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FEATURES IsoLogicTM Circuit Architecture Isolation Test Voltage: To 3.5 kV rms Five Isolated Logic Lines: Available in Six I/O Configurations Logic Signal Bandwidth: 20 MHz (Min), 40 mbps (NRZ) Isolated Power Transformer: 37 V p-p, 1.5 W Max CMV Transient Immunity: 10 kV/ s Min Waveform Edge Transmission Symmetry: 1 ns Field and System Output Enable/Three-State Functions Performance Rated Over -25 C to +85 C UL1950, IEC950, EN60950 Certification, Pending APPLICATIONS PLC/DCS Analog Input and Output Cards Communications Bus Isolation General Data Acquisition Applications IGBT Motor Drive Controls High Speed Digital I/O Ports GENERAL DESCRIPTION
High Speed, Logic Isolator with Power Transformer AD260
FUNCTIONAL BLOCK DIAGRAM
AD260
F0 18
T TR IS IST TAT AT E E
LATCH
LINE 0
D E LATCH
1
S0
F1 19
TR IST AT E
LINE 1
D E LATCH
2
S1
F2 20
TR IST AT E
LINE 2
D E
3
S2
LATCH
F3 21
D E LATCH
LINE 3
E AT IST TR
4
S3
F4 22
D E
LINE 4
E AT IST TR
5
S4
ENABLEFLD 17 +5Vdc 5Vdc RTN 17V p-p OUT CT OUT 17V p-p OUT +5Vdc 5Vdc RTN DRIVE +5V DRIVE
6
ENABLESYS +5VdcSYS 5V RTNSYS DRVA DRVCT DRVB
+5VdcFLD 16 5V RTNFLD 15 PWRAFLD 14 PWRCTFLD 13 PWRBFLD 12
7
8
The AD260 is designed using Analog Devices new IsoLogic circuit architecture to isolate five digital control signals to/ from a microcontroller and its related field I/O components. Six models allow all I/O combinations from five input lines to five output lines, including combinations in between. Every AD260 effectively replaces up to five opto-isolators while also providing the 1.5 W transformer for a 3.5 kV isolated dc-dc power supply circuit. Each line of the AD260 has a bandwidth of 20 MHz (min) with a propagation delay of only 14 ns, which allows for extremely fast data transmission. Output waveform symmetry is maintained to within 1 ns of the input so the AD260 can be used to accurately isolate time-based PWM signals. All field or system output pins of the AD260 can be set to a high resistance three-state level by use of the two enable pins. A field output three-stated offers a convenient method of presetting logic levels at power-up by use of pull-up/down resistors. System side outputs being three-stated allows for easy multiplexing of multiple AD260s. The isolation barrier of the AD260 B Grade is 100% tested at 3.5 kV rms (system to field). The barrier design also provides excellent common-mode transient immunity from 10 kV/s common-mode voltage excursions of field side terminals relative to the system side, with no false output triggering on either side. Each output is updated within nanoseconds by input logic transitions, the AD260 also has a continuous output update feature that automatically updates each output based on the dc level of
IsoLogic is a trademark of Analog Devices, Inc.
9 10 11
FIELD
SYSTEM
the input. This guarantees the output is always valid 10 s after a fault condition or after the power-up reset interval. The AD260 also has an integral center tap transformer for generating isolated power. Typically driven by a 5 V push-pull drive at the primary, it will generate a 37 V p-p output capable of supplying up to 1.5 W. This can then be regulated to the desired voltage, including 5 V dc for circuit components and 24 V for a 20 mA loop supply when needed.
PRODUCT HIGHLIGHTS
Six Isolated Logic Line I/O Configurations Available: The AD260 is available in six pin-compatible versions of I/O configurations to meet a wide variety of requirements. Wide Bandwidth with Minimal Edge Error: The AD260 with IsoLogic affords extremely fast isolation of logic signals due to its 20 MHz bandwidth and 14 ns propagation delay. It maintains a waveform input-to-output edge transition error of typically less than 1 ns (total) for positive vs. negative transition. 3.5 kV rms Test Voltage Isolation Rating: The AD260 B Grade is rated to operate at 1.25 kV rms and is 100% production tested at 3.5 kV rms, using a standard ADI test method. High Transient Immunity: The AD260 rejects commonmode transients slewing at up to 10 kV/s without false triggering or damage to the device.
(Continued on page 6)
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Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 (c) Analog Devices, Inc., 1998
AD260-SPECIFICATIONS (Typical at T = +25 C, +5 V dc
A
SYS,
+5 V dcFLD, tRR = 50 ns max unless otherwise noted)
Min Typ Max Units
Parameter INPUT CHARACTERISTICS Threshold Voltage Positive Transition (VT+) Negative Transition (VT-) Hysteresis Voltage (VH) Input Capacitance (CIN) Input Bias Current (IIN) OUTPUT CHARACTERISTICS Output Voltage1 High Level (VOH) Low Level (VOL) Output Three-State Leakage Current DYNAMIC RESPONSE (Refer to Figure 2) Max Logic Signal Frequency (fMIN) Waveform Edge Symmetry Error (tERROR) Logic Edge Propagation Delay (tPHL, tPLH) Minimum Pulsewidth (tPWMIN) Max Output Update Delay on Fault or After Power-Up Reset Interval ( 30 s)2 ISOLATION BARRIER RATING Operating Isolation Voltage (VCMV) Isolation Rating Test Voltage (VCMV TEST)4 Transient Immunity (VTRANSIENT) Isolation Mode Capacitance (CISO) Capacitive Leakage Current (ILEAD) POWER TRANSFORMER Primary Winding Inductance (LP) Number of Turns (NP) Resistance Max Volt-Seconds (E x t) Recommended Operating Frequency Absolute Min Operating Frequency Secondary Winding Number of Turns (NS) Resistance Insulation Withstand (VCMV TEST) Capacitance Recommended Max Power POWER SUPPLY Supply Voltage (+5 V dcSYS and +5 V dcFLD) Power Dissipation Capacitance Quiescent Supply Current Supply Current TEMPERATURE RANGE Rated Performance (TA)5 Storage (TSTG)
3 1
Conditions
+5 V dcSYS = 4.5 V +5 V dcSYS = 5.5 V +5 V dcSYS = 4.5 V +5 V dcSYS = 5.5 V +5 V dcSYS = 4.5 V +5 V dcSYS = 5.5 V Per Input
2.0 3.0 0.9 1.2 0.4 0.5
2.7 3.2 1.8 2.2 0.9 1.0 5 0.5
3.15 4.2 2.2 3.0 1.4 1.5
V V V V V V pF A
+5 V dcSYS = 4.5 V, |IO| = 0.02 mA +5 V dcSYS = 4.5 V, |IO| = 4 mA +5 V dcSYS = 4.5 V, |IO| = 0.02 mA +5 V dcSYS = 4.5 V, |IO| = 4 mA ENABLESYS/FLD @ Logic Low/High Level Respectively 50% Duty Cycle, +5 V dcSYS = 5 V tPHL vs. tPLH
4.4 3.7 0.1 0.4 0.5 20
V V V V A MHz ns ns ns s
1 14
25
25 12 AD260A AD260B AD260A AD260B Total Capacitance, All Lines and Transformer 240 V rms @ 60 Hz Bifilar Wound, Center-Tapped Each Half Each Half Each Half Each Half -25C to +85C, Push-Pull Drive -25C to +85C, Push-Pull Drive Bifilar Wound, Center-Tapped Each Half Each Half Primary to Secondary Primary to Secondary Rated Performance Rated Performance Operating Effective, per Input, Either Side Effective per Output, Either Side--No Load Each, +5 V dcSYS & FLD All Lines @ 10 MHz (Sum of +5 V dcSYS & FLD) 375 1250 1750 3500 10,000 14 18 2
V rms V rms V rms V rms V/s pF A rms
1 26 0.6 150 75 200 27 300
mH Turns V x s kHz kHz Turns V rms pF W V dc V dc pF pF mA mA C C
48 2.3 3,500 5 1.0 4.5 4.0 8 28 4 18 -25 -40 +85 +85 1.5 5.5 5.75
NOTES 1 For best performance, bypass +5 V dc supplies to com. at or near the device (0.01 F). +5 V dc supplies are also internally bypassed with 0.05 F. 2 As the supply voltage is applied to either side of the AD260, the internal circuitry will go into a power-up reset mode (all lines disabled) for about 30 s after the point where +5 V dcSYS & FLD passes above 3.3 V. 3 "Operating" isolation voltage is derived from the Isolation Test Voltage in accordance with such methods as found in VDE-0883 wherein a device will be "hi-pot" tested at twice the operating voltage, plus one thousand volts. Partial discharge testing, with an acceptance threshold of 80 pC of discharge may be considered the same as a hi-pot test (but nondestructive). 4 Partial Discharge at 80 pC THLD. 5 Supply Current will increase slightly, but otherwise the unit will function within specification to - 40C. Specifications are subject to change without notice.
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AD260
ABSOLUTE MAXIMUM RATINGS* Parameter Supply Voltage (+5 V dcSYS & FLD) DC Input Voltage (VIN MAX) DC Output Voltage (V OUT MAX) Clamp Diode Input Current (I IK) Clamp Diode Output Current (I OK) Output DC Current, per Pin (I OUT) DC Current, VCC or GND (ICC or IGND) Storage Temperature (T STG) Lead Temperature (Soldering, 10 sec) Electrostatic Protection (V ESD) Conditions Referred to +5 V dcSYS & FLD and 5 V RTNSYS & FLD Respectively Referred to +5 V RTNSYS & FLD and 5 V dcSYS & FLD Respectively For VI < -0.5 V or VI > 5 V RTNSYS & FLD +0.5 V For VO < -0.5 V or VO > 5 V RTNSYS & FLD +0.5 V Min -0.5 -0.5 -0.5 -25 -25 -25 -50 -40 4.5 5 Typ Max +6.0 +0.5 +0.5 +25 +25 +25 +50 +85 +300 Units V V V mA mA mA mA C C kV
Per MIL-STD-883, Method 3015
*Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum ratings for extended periods may effect device reliability.
I/O CONFIGURATIONS AVAILABLE
PIN CONFIGURATION
1 2 3 4 5 6 7 8 9 10 11
The AD260 is available in several configurations. The choice of model is determined by the desired number of input vs. output lines. All models have identical footprints with the power and enable pins always being in the same locations.
PIN FUNCTION DESCRIPTIONS Pin 1-5* 6 7 8 9-14 15 16 17 18-22* Mnemonic S0 Through S4 ENABLESYS +5 V dcSYS 5 V RTNSYS Function
SYSTEM
Digital Xmt or Rcv from F0 Through F4 System Output Enable/Three-State System Power Supply (+5 V dc Input) System Power Supply Common Not Present On Unit 5 V RTNFLD Field Power Supply Common Field Power Supply (+5 V Input) +5 V dcFLD Field Output Enable/Three-State ENABLEFLD F0 Through F4 Digital Xmt or Rcv from S0 Through S4
S0 S1 S2 S3 S4 ENABLESYS +5VdcSYS 5V RTNSYS DRVA DRVCT DRVB
BOTTOM VIEW PWRBFLD PWRCTFLD PWRAFLD 5V RTNFLD +5VdcFLD ENABLEFLD F0 F1 F2 F3 F4
12 13 14 15 16 17 18 19 20 21 22
FIELD
*Function of pin determined by model. Refer to Table I.
Caution: Use care in handling unit as contaminants on the bottom side of the unit or the circuit card to which it is mounted will lead to reduced breakdown voltage across the isolation barrier.
ORDERING GUIDE
Model Number
AD260AND-0 AD260AND-1 AD260AND-2 AD260AND-3 AD260AND-4 AD260AND-5 AD260BND-0 AD260BND-1 AD260BND-2 AD260BND-3 AD260BND-4 AD260BND-5
Description
0 Inputs, 5 Outputs 1 Input, 4 Outputs 2 Inputs, 3 Outputs 3 Inputs, 2 Outputs 4 Inputs, 1 Output 5 Inputs, 0 Outputs 0 Inputs, 5 Outputs 1 Input, 4 Outputs 2 Inputs, 3 Outputs 3 Inputs, 2 Outputs 4 Inputs, 1 Output 5 Inputs, 0 Outputs
Isolation Test Voltage
1.75 kV rms 1.75 kV rms 1.75 kV rms 1.75 kV rms 1.75 kV rms 1.75 kV rms 3.5 kV rms 3.5 kV rms 3.5 kV rms 3.5 kV rms 3.5 kV rms 3.5 kV rms
Package Description
Plastic DIP Plastic DIP Plastic DIP Plastic DIP Plastic DIP Plastic DIP Plastic DIP Plastic DIP Plastic DIP Plastic DIP Plastic DIP Plastic DIP
Package Option
ND-22 ND-22 ND-22 ND-22 ND-22 ND-22 ND-22 ND-22 ND-22 ND-22 ND-22 ND-22
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD260 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
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-3-
AD260
PIN CONFIGURATIONS AD260BND-0 AD260BND-2
AD260-0
F0 18
TR TR IIST SA ATE TE
LATCH
AD260-2
1
LATCH
LINE 0 - OUT
D E LATCH
S0
F0 18
TR TR IIST SA ATE TE
LINE 0 - OUT
D E LATCH
1
S0
F1 19
TR IST AT E
LINE 1 - OUT
D E LATCH
2
S1
F1 19
TR IST AT E
LINE 1 - OUT
D E LATCH D E
2
S1
F2 20
TR IST AT E
LINE 2 - OUT
D E LATCH
3
S2
F2 20
TR IST AT E
LATCH
LINE 2 - OUT
3
S2
F3 21
TR IST AT E
LINE 3 - OUT
D E LATCH
4
S3
F3 21
D E LATCH
LINE 3 - IN
E AT IST TR
4
S3
F4 22
TR IST AT E
LINE 4 - OUT
D E
5
S4
F4 22
D E
LINE 4 - IN
E AT IST TR
5
S4
ENABLEFLD 17 +5Vdc 5Vdc RTN 17V p-p OUT CT OUT 17V p-p OUT +5Vdc 5Vdc RTN DRIVE +5V DRIVE
6
ENABLESYS +5VdcSYS 5V RTNSYS DRVA
ENABLEFLD 17 +5Vdc 5Vdc RTN 17V p-p OUT CT OUT 17V p-p OUT +5Vdc 5Vdc RTN DRIVE +5V DRIVE
6
ENABLESYS +5VdcSYS 5V RTNSYS DRVA DRVCT DRVB
+5VdcFLD 16 5V RTNFLD 15 PWRAFLD 14 PWRCTFLD 13 PWRBFLD 12
7
+5VdcFLD 16 5V RTNFLD 15 PWRAFLD 14 PWRCTFLD 13 PWRBFLD 12
7
8
8
9
9 10 11
10 DRVCT 11 DRVB
FIELD
SYSTEM
FIELD
SYSTEM
AD260BND-1
AD260BND-3
AD260-1
F0 18
TR TR IIST SA ATE TE
LATCH
AD260-3
1
LATCH
LINE 0 - OUT
D E LATCH
S0
F0 18
TR TR IIST SA ATE TE
LINE 0 - OUT
D E LATCH
1
S0
F1 19
TR IST AT E
LINE 1 - OUT
D E LATCH
2
S1
F1 19
TR IST AT E
LATCH
LINE 1 - OUT
D E
2
S1
F2 20
TR IST AT E
LINE 2 - OUT
D E LATCH
3
S2
F2 20
D E LATCH
LINE 2 - IN
E AT IST TR
3
S2
F3 21
TR IST AT E
LINE 3 - OUT
D E
4
S3
F3 21
D E LATCH
LINE 3 - IN
E AT IST TR
4
S3
LATCH
F4 22
D E
LINE 4 - IN
E AT IST TR
5
S4
F4 22
D E
LINE 4 - IN
E AT IST TR
5
S4
ENABLEFLD 17 +5Vdc 5Vdc RTN 17V p-p OUT CT OUT 17V p-p OUT +5Vdc 5Vdc RTN DRIVE +5V DRIVE
6
ENABLESYS
ENABLEFLD 17 +5Vdc 5Vdc RTN 17V p-p OUT CT OUT 17V p-p OUT +5Vdc 5Vdc RTN DRIVE +5V DRIVE
6
ENABLESYS +5VdcSYS 5V RTNSYS DRVA DRVCT DRVB
+5VdcFLD 16 5V RTNFLD 15 PWRAFLD 14 PWRCTFLD 13 PWRBFLD 12
7
+5VdcSYS 5V RTNSYS DRVA DRVCT DRVB
+5VdcFLD 16 5V RTNFLD 15 PWRAFLD 14 PWRCTFLD 13 PWRBFLD 12
7
8
8
9 10 11
9 10 11
FIELD
SYSTEM
FIELD
SYSTEM
-4-
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AD260
PIN CONFIGURATIONS AD260BND-4 AD260BND-5
AD260-4
F0 18
TR TR IIST SA ATE TE
LATCH
AD260-5
1
LATCH D E LATCH
LINE 0 - OUT
D E
S0
F0 18
LINE 0 - IN
E AT IST TR
1
S0
LATCH
F1 19
D E LATCH
LINE 1 - IN
E AT IST TR
2
S1
F1 19
D E LATCH
LINE 1 - IN
E AT IST TR
2
S1
F2 20
D E LATCH
LINE 2 - IN
E AT IST TR
3
S2
F2 20
D E LATCH
LINE 2 - IN
E AT IST TR
3
S2
F3 21
D E LATCH
LINE 3 - IN
E AT IST TR
4
S3
F3 21
D E LATCH
LINE 3 - IN
E AT IST TR
4
S3
F4 22
D E
LINE 4 - IN
E AT IST TR
5
S4
F4 22
D E
LINE 4 - IN
E AT IST TR
5
S4
ENABLEFLD 17 +5Vdc 5Vdc RTN 17V p-p OUT CT OUT 17V p-p OUT +5Vdc 5Vdc RTN DRIVE +5V DRIVE
6
ENABLESYS +5VdcSYS 5V RTNSYS DRVA
ENABLEFLD 17 +5Vdc 5Vdc RTN 17V p-p OUT CT OUT 17V p-p OUT +5Vdc 5Vdc RTN DRIVE +5V DRIVE
6
ENABLESYS +5VdcSYS 5V RTNSYS DRVA DRVCT DRVB
+5VdcFLD 16 5V RTNFLD 15 PWRAFLD 14 PWRCTFLD 13 PWRBFLD 12
7
+5VdcFLD 16 5V RTNFLD 15 PWRAFLD 14 PWRCTFLD 13 PWRBFLD 12
7
8
8
9
9 10 11
10 DRVCT 11 DRVB
FIELD
SYSTEM
FIELD
SYSTEM
Table I.
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
AD260BND-0 S0 (Xmt) S1 (Xmt) S2 (Xmt) S3 (Xmt) S4 (Xmt) ENABLESYS +5 V dcSYS 5 V RTNSYS DRVA DRVCT DRVB PWRBFLD PWRCTFLD PWRAFLD 5 V RTNFLD +5 V dcFLD ENABLEFLD F0 (Rcv) F1 (Rcv) F2 (Rcv) F3 (Rcv) F4 (Rcv)
AD260BND-1 S0 (Xmt) S1 (Xmt) S2 (Xmt) S3 (Xmt) S4 (Rcv) * * * * * * * * * * * * F0 (Rcv) F1 (Rcv) F2 (Rcv) F3 (Rcv) F4 (Xmt)
AD260BND-2 S0 (Xmt) S1 (Xmt) S2 (Xmt) S3 (Rcv) S4 (Rcv) * * * * * * * * * * * * F0 (Rcv) F1 (Rcv) F2 (Rcv) F3 (Xmt) F4 (Xmt)
AD260BND-3 S0 (Xmt) S1 (Xmt) S2 (Rcv) S3 (Rcv) S4 (Rcv) * * * * * * * * * * * * F0 (Rcv) F1 (Rcv) F2 (Xmt) F3 (Xmt) F4 (Xmt)
AD260BND-4 S0 (Xmt) S1 (Rcv) S2 (Rcv) S3 (Rcv) S4 (Rcv) * * * * * * * * * * * * F0 (Rcv) F1 (Xmt) F2 (Xmt) F3 (Xmt) F4 (Xmt)
AD260BND-5 S0 (Rcv) S1 (Rcv) S2 (Rcv) S3 (Rcv) S4 (Rcv) * * * * * * * * * * * * F0 (Xmt) F1 (Xmt) F2 (Xmt) F3 (Xmt) F4 (Xmt)
*Pin function is the same on all models, as shown in the AD260BND-0 column.
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-5-
AD260
(Continued from page 1)
Integral Isolated Power: The AD260 includes an integral, uncommitted and flexible 1 Watt power transformer for developing isolated field power sources. Field and System Enable Functions: Both the isolated and nonisolated sides of the AD260 have ENABLE pins that threestate all outputs. Upon reenabling these pins, all outputs are updated to reflect the current input logic level. CE Certifiable: Simply by adding the external bypass capacitors at the supply pins, the AD260 can attain CE certification in most applications (to the EMC directive) and conformance to the low voltage (safety) directive is assured by the EN60950 certification.
GENERAL ATTRIBUTES
Edge "fidelity," or the difference in propagation time for rising and falling edges, is typically less than 1 ns. Power consumption, unlike opto-isolators, is a function of operating frequency. Each logic line barrier driver requires about 160 A per MHz and each receiver 40 A per MHz plus, of course, 4 mA total idle current (each side). The supply current diminishes slightly with increasing temperature (about -0.03%/C). The total capacitance spanning the isolation barrier is less than 10 pF. The minimum width of a pulse that can be accurately coupled across the barrier is about 25 ns. Therefore the maximum square-wave frequency of operation is 20 MHz. Logic information is sent across the barrier as "set-hi/set-lo" data that is derived from logic level transitions of the input. At power-up or after a fault condition, an output might not represent the state of the respective channel input to the isolator. An internal circuit operates in the background which interrogates all inputs about every 5 s and in the absence of logic transitions, sends appropriate "set-hi" or "set-lo" data across the barrier. Recovery time from a fault condition or at power-up is thus between 5 s and 10 s.
SCHMITT TRIGGER DATA IN 3.5kV DATA ISOLATION DATA OUTPUT TRANSMITTER BARRIER RECEIVER BUFFER DQ OUT ENABLE CONTINUOUS UPDATE CIRCUIT
The AD260 provides five HCMOS/ACMOS compatible isolated logic lines with 10 kV/s common-mode transient immunity. The case design and pin arrangement provides greater than 18 mm spacing between field and system side conductors, providing CSA/IS and IEC creepage spacing consistent with 750 V mains isolation. The five unidirectional logic lines have six possible combinations of "ins" and "outs," or transmitter/receiver pairs; hence there are six AD260 part configurations (see Table I). Each 20 MHz logic line has a Schmidt trigger input and a threestate output (on the other side of the isolation barrier) and 14 ns of propagation delay. A single enable pin on either side of the barrier causes all outputs on that side to go three-state and all inputs (driven pins) to ignore their inputs and retain their last known state. Note: All unused logic inputs (1-5) should be tied either high or low, but not left floating.
ENABLE
G GATED TRANSPARENT LATCH
Figure 1. Simplified Block Diagram
PROPAGATION DELAY
POSITIVE GOING INPUT THRESHOLD INPUT +3V +2V NEGATIVE GOING INPUT THRESHOLD HYSTERESIS
OUTPUT
63% 37%
tPD tPLH
tPD tPHL
t ff
EFFECTIVE CIRCUIT MODEL FOR ONE ISOLATED LOGIC LINE
SCHMITT TRIGGER DELAY LINE 12.5ns 5pF INPUT CAPACITANCE BUFFER 100 5pF OUTPUT CAPACITANCE
tPD
t rr = tff = 100 x CTOTAL OUTPUT CAPACITANCE
0.5ns - NO LOAD = 5.5ns INTO 50pF
TOTAL DELAY = (tPLH OR tPHL) = tPD + (trr OR tff)
13ns (NO LOAD), 18ns (50pF LOAD)
Figure 2. Typical Timing and Delay Models
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AD260
The power transformer is designed to operate between 150 kHz and 250 kHz and will easily deliver more than 1 W of isolated power when driven push-pull (5 V) on the system side. Different transformer tap, rectifier and regulator schemes will provide combinations of 5 V, 15 V, 24 V or even 30 V or higher. The output voltage when driven with a low voltage-drop drive (@ 5 V push-pull) will be 37 V p-p across the entire secondary. This will drop to 33 V p-p at 4.5 V drive.
+5Vdc 4.7k 9 15 16 COMP VIN VREF 12 11 52T CT LM2524 + - 3.3 F TANT. 13 14 GND 8 INV NI 10 1 2 0.1 F CL+ CL- 4 5
VOUT @ 5V DRIVE +8.55 V(MIN) @ 4.5V DRIVE 7.62 +5Vdc/+4.5Vdc 150mA
Application Examples
The following is an example of a typical transformer system-side drive circuit and a field-side regulation circuit suitable for use in most general applications.
VDD FLD +5V ISO +5V REG
96T CT.
ENABLE FLD (PWR-UP ENABLE)
I LOGIC/SHUTDOWN (H I ) -5V ISO -5V REG
Figure 4.
3.3k RT 6 7 C
T
+
80mA LOAD COM
a
470pF
+5Vdc 6 1 D1 MAX 253 8 SD 4 SHUTDOWN (ON/OFF)
a
+ -
b b
+5Vdc/+4.5Vdc 150mA
52T CT
20mA 17.63 15.79 20mA
+ -
3.3 F TANT. D2 G1
FS G2 7 2
3
COM
+
a a
Figure 3. System Side Transformer Driver Examples
40mA
+5Vdc/+4.5Vdc 150mA
-
40mA 8.64 7.72 COM
a a
+
+26.3 +8.64 23.5 20mA 7.72 20mA COM
b a
+5Vdc/+4.5Vdc 150mA
+
b
"a" DIODES "b" DIODES
IN5818/MBR0530 IN5819/MBR0540
Figure 5. Field Side Power Supply Rectifier Examples
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AD260
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
22-Lead Plastic DIP (ND-22)
0.550 (13.97) MAX 0.440 (11.18) MAX
22
1.500 (38.1) MAX
SIDE VIEW
1 11 12
END VIEW
0.160 (4.06) 0.140 (3.56) 0.075 (1.91)
0.050 (1.27)
0.020 0.010 (0.508 0.254) 22 PLACES
0.100 (2.54)
0.350 (8.89)
PIN 1 BOTTOM VIEW 0.5* (12.2)
FIELD
0.250 (6.35)
SYSTEM
0.050 (1.27) 0.350 (8.89) * CREEPAGE PATH (SUBTRACT APPROXIMATELY 0.079 (2mm) FOR SOLDER PAD RADII ON PC BOARD. THIS SPACING SUPPORTS THE INTRINSICALLY SAFE RATING OF 750V. WAVE SOLDERING IS NOT RECOMMENDED.
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PRINTED IN U.S.A.
C3031-8-9/98

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